RTL-Based Modeling and Verification of a Three-Channel Package-Scale Galvanic Isolation Interface for Wide-Bandgap Gate Drivers

Paper ID: EIJTEM_2026_13_3_165-176

Author's Name: N. Bhavana, Rajashekar Kakoju, Radaram Mahesh, Edudula Manisha,

Volume: 13

Issue: 3

Year: 2026

Page No: 165-176

Abstract:

Wide-bandgap power switches require gate-driver interfaces that combine reinforced galvanic isolation, low propagation delay, diagnostic communication, and robust fault behavior. This paper presents an RTL-based digital and behavioral realization of a three-channel package-scale galvanic isolation interface inspired by RF-coupled co-packaged microantenna architectures. The proposed model separates the physical radio-frequency isolation barrier from its digital control plane and implements three independent paths: a direct controller-to-driver PWM channel, an edge-coded reverse power-control channel, and a half-duplex bidirectional diagnostic channel. The design additionally incorporates programmable channel delay, safe-low fault injection, transmitter mutual exclusion, timeout recovery, and a four-bit offset-calibration controller. The power-control channel encodes rising and falling PWM transitions using short and long pulses, respectively, while the receiver reconstructs the PWM state through pulse-width classification. The diagnostic controller uses a finite-state machine with idle, query, turnaround, response, and recovery states to prevent simultaneous transmission across a shared isolation channel. A self-checking Verilog testbench verifies forward and reverse communication, edge-code reconstruction, direction switching, channel-fault response, and calibration convergence. The resulting platform provides a synthesizable digital foundation for mixed-signal co-design, FPGA prototyping, and pre-silicon verification of package-scale isolation interfaces for SiC and GaN gate-driver applications.

Keywords: galvanic isolation, wide-bandgap gate driver, SiC, GaN, on-off keying, half-duplex communication, edge coding, Verilog, RTL verification, fault-tolerant interface.

References:

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