Efficient VLSI Implementation of Hybrid LDPC-STBC Codes for Enhanced Satellite Communication Systems

Paper ID: EIJTEM_2026_13_3_1-5

Author's Name: Aluvala Sravankumar, Dr. D. Naga Sudha

Volume: 13

Issue: 3

Year: 2026

Page No: 1-5

Abstract:

Satellite communication systems require reliable and hardware-efficient error control techniques because the transmitted data is commonly affected by noise, fading, interference and attenuation. This paper presents an efficient VLSI implementation of a hybrid Low-Density Parity-Check (LDPC) and Space-Time Block Coding (STBC) scheme for enhanced satellite communication systems. The methodology follows a two-level coding approach in which LDPC coding provides strong error correction through sparse parity-check based encoding and iterative decoding, while STBC improves link reliability by exploiting spatial diversity in multiple-antenna transmission. The design is implemented and evaluated using Xilinx Vivado on a Zynq-7000 device. The results taken from the thesis show that, for N = 32, the proposed method reduces LUT utilization from 104 to 6, total power from 34.692 W to 17.134 W and total delay from 18.142 ns to 14.766 ns. For N = 64, LUT utilization is reduced from 208 to 13 and total power is reduced from 69.384 W to 25.69 W. The results demonstrate that the hybrid LDPC-STBC architecture provides a compact and energy-efficient VLSI solution for reliable satellite communication.

Keywords: LDPC, STBC, VLSI, satellite communication, error correction code, Xilinx Vivado, Zynq-7000

References:

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