Transaction-Level Design and Verification of a Hybrid AMBA AXI4-Lite/ACE Interconnect for Scalable Heterogeneous SoCs

Paper ID: EIJTEM_2026_13_3_157-164

Author's Name: T. Leelavathi, Abdul Maqseed Shaik, Manga Rajalaxmi, Cheguri Mahesh

Volume: 13

Issue: 3

Year: 2026

Page No: 157-164

Abstract:

Modern heterogeneous systems-on-chip require both lightweight register access and coherent shared-memory communication, yet these needs are often discussed as if AXI4-Lite and ACE were a single protocol layer. This paper presents a transaction-level architecture that deliberately separates an AXI4-Lite control plane from an ACE/ACE-Lite coherent data plane while sharing address-routing, arbitration, response-handling, monitoring, and verification services. The architecture targets CPU cores, accelerators, DMA engines, memory controllers, and memory-mapped peripherals. A deterministic cycle-abstract reference model is used to evaluate class-aware round-robin arbitration, filtered snooping, error responses, back-pressure, and cache-visible data consistency before RTL implementation. Verification covers 100,000 randomized address/response transactions, 20,000 cycles of continuous four-master contention, and 50,000 coherent memory operations, with no decode, response, mutual-exclusion, or stale-read violations in the reference model. At an offered load of 0.12 transactions/cycle, the proposed split-plane architecture reduces mean latency by 40.6%, 50.7%, and 76.3% for control-dominant, balanced, and memory-dominant mixes, respectively, compared with a serialized fixed-priority/broadcast-snoop baseline. Filtered snooping reduces peer snoop probes by 52.2–57.7%. A balanced-load sweep further shows that the baseline saturates near 0.154 transactions/cycle, whereas the proposed model sustains approximately 0.178 transactions/cycle at an offered load of 0.18. The results establish a reproducible architectural baseline for subsequent System Verilog/UVM implementation and FPGA/ASIC evaluation.

Keywords: AMBA, AXI4-Lite, ACE, ACE-Lite, system-on-chip, cache coherency, transaction-level modeling, UVM, interconnect, arbitration.

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