DESIGN OF EIZAKKAR COMPARATOR FOR HIGH SPEED AND LOW POWER CONSUMPTION USING CMOS TECHNOLOGY

Paper ID: EIJTEM_2022_9_4_107-115

Author's Name: Dr.B. Satheesh, Dr.G.Koteswara Rao

Volume: 9

Issue: 4

Year: 2022

Page No: 107-115

Abstract:

The aim of this Research proposal is to design and build dynamic comparator that outperforms the conventional Strong-Arm latch (single tail comparator and double-tail latched comparator) in terms of delay and power efficiency. A comparator plays an important role in designing the desired high-resolution, high-speed and low power analog-to-digital data converter. Among different architectures, CMOS dynamic latched comparators find wide usage in Analog-to-Digital Converters (ADCs) thanks to their high-speed, low power consumption and ability to produce rail-to-rail outputs. The Strong-Arm latch is one of the most common dynamic comparators used in ADC designs. In this Research proposal, an EI-zakker comparator for high speed and low-power dynamic comparator topology is proposed and compared to the conventional Strong ARM latch type of single tail and double tail latch in terms of delay, power consumption and speed. Simulation results show that the proposed architectures consume 40% to 50% less power than the Strong-Arm latch for the same input referred voltage of 1.8v. Additionally, the speed of proposed EI-Zakker comparator design is insensitive to input common-mode variation and outperforms the Strong-Arm latch type for low Vcm (common mode voltage) values. The Strong-Arm latch types and proposed EI-Zakker comparator architecture are simulated on the same technology using 180nm TSMC CMOS Technology. The measurement results confirmed the better performance of the proposed designs by showing 46% less power consumption than the Strong-Arm latch type of single tail and double tail comparators with similar input-referred voltage. The proposed EI-Zakker topology offers a low-power, wide common-mode input range solution for high-precision comparator design.

Keywords: Comparator, Strong ARM comparator, CMOS, EI-Zakker comparator, double tail latch type comparator, low power.

References:

[1] B. Goll and H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65, “IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 56, no 11, pp. 810-814, Nov. 2009.
[2] H. Jeon, “Low-power high-speed low-offset fully dynamic CMOS latched comparator,” Master’s thesis, Northeastern University, Boston, Massachusetts, 2010.
[3] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed Optimization of a latch-type voltage séance amplifier.” IEEE J. Solid State circuits, vol. 39, no.7, pp. 1148-1158, Jul. 2004
[4] D. Schinkel et. al, "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup Hold Time", 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, 2007, pp. 314 605.
[5] H. S. Bindra, C. E. Lokin, D. Schinkel, A. J. Annema, and B. Nauta, “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise,” IEEE Journal of Solid-State Circuits, vol.53, no.7, pp.1902–1912, July2018.
[6] M. van EIzakker et.al, "A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1MS/s", in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
[7] TSMC 180nm Process Design Kit Documentation.
[8] R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation.
[9] B. Goll and H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for supply voltagesdown to 0.65, “IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 56, no 11, pp. 810-814, Nov. 2009.
[10] Heung Jun Jeon and Yong-Bin Kim, “A Novel Low-Power, Low-Offset and High-Speed CMOS Dynamic Latched Comparator”, IEEE, 2010.
[11] Razavi Behzad, “Design of Analog CMOS Integrated Circuits”, New York, NY: McGraw-Hill, Inc., 2000.
[12] Sansen Willy M.C., Analog Design Essentials”, Neatherlands, Springer International Edition, 2006.
[13] Dutta Ramen, “CMOS Voltage Comparator”, Advanced VLSI Design Lab, IIT Kharagpur. [Online]. Available: conf05.iitkgp.ac.in/avlsi/logf/summer course/2008/c omparator.pdf [Accessed: 14 March, 2011].
[14] Allen Phillip E., Short Course Notes on CMOS Analog IC Design. [Online]. Available: http://www.aicdesign.org/scnotes10.html [Accessed: February 12, 2011].
[15] Allen Phillip E., “Lecture-360- Characterization of Comparator”. [Online]. Available: users.ece.gatech.edu/pallen/.../L360-Char_Comparators-2UP.pdf [Accessed 20 February, 2011].

View PDF