Enhanced Data Transmission in Communication Systems Using Optimized QC-LDPC Codes for Robust Error Detection and Correction

Paper ID: EIJTEM_2025_12_4_215-221

Author's Name: Senthil Kumar M, Sapthagiri Vienala

Volume: 12

Issue: 4

Year: 2025

Page No: 215-221

Abstract:

The transmission of data through advanced space communication channels is often degraded by various types of noise and interference, leading to burst errors that severely affect communication reliability. Traditional Hamming encoders and decoders are limited in capability, as they can only detect and correct single-bit errors, making them unsuitable for high-noise environments such as deep-space links. To address this limitation, this work implements Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes, which offer superior error detection and correction capabilities for multiple-bit errors. The QC-LDPC encoding process employs a generator matrix incorporating both parity and identity submatrices, producing structured codewords that enhance encoding efficiency and reduce hardware complexity. These encoded codewords are transmitted over space communication channels characterized by high interference and bit corruption. At the receiver end, a QC-LDPC decoding process utilizing syndrome computation, error localization, and iterative correction algorithms effectively restores the integrity of the transmitted data. Simulation results demonstrate that the proposed QC-LDPC-based system achieves significant performance improvements compared to conventional LDPC schemes, particularly in terms of bit error rate (BER) reduction, throughput, and robustness under burst noise conditions.

Keywords: Error Detection, Error Correction, LDPC, Xilinx, FPGAs

References:

[1]. Somashekhar, Vikas Maheshwari, and R. P. Singh. "A Study of Fault Tolerance In High Speed VLSI Circuits." International Journal Of Scientific & Technology Research 8.08 (2019).
[2]. Palchaudhuri, Ayan, and Anindya Sundar Dhar. "Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support." Journal of Parallel and Distributed Computing 151 (2021): 13-23.
[3]. Sharma, Vishal, et al. "A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes." Analog Integrated Circuits and Signal Processing 107.2 (2021): 339-352.
[4]. Tavakkolai, Hamid, Gholamreza Ardeshir, and Yasser Baleghi. "Fast adder with the ability of multiple faults detection and correction." International Journal of Nonlinear Analysis and Applications 12.Special Issue (2021): 937-950.
[5]. Maiti, Swapan, Meghna Sengupta, and Dipanwita Roy Chowdhury. "Generating nonlinear codes for multi-bit symbol error correction using cellular automata." Physica D: Nonlinear Phenomena 415 (2021): 132758.
[6]. Abbas, S. M., Tonnellier, T., Ercan, F., & Gross, W. J. (2020, October). High-throughput VLSI architecture for GRAND. In 2020 IEEE Workshop on Signal Processing Systems (SiPS) (pp. 1-6). IEEE.
[7]. Sai, G. Manoj, et al. "Diagonal hamming based multi-bit error detection and correction technique for memories." 2020 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2020.
[8]. Satyanarayana, Telugu, Vaseen Ahmed Qureshi, and G. Divya. "Design and implementation of error detection and correction system for semiconductor memory applications." (2022): 325-330.
[9]. Flayyih, Wameedh Nazar. "Crosstalk aware multi-bit error detection with limited error correction coding for reliable on-chip communication." International Journal of Computer Applications 179.40 (2018).
[10]. Tripathi, S., Jana, J., Samanta, J., Raj, A., Ranjan, D., & Singh, M. P. (2020). Design and evaluation of neale-based multi-bit adjacent error-correcting codec for sram. In Proceedings of the 2nd International Conference on Communication, Devices and Computing (pp. 259-268). Springer, Singapore.
[11]. Sharma, V., Bisht, P., Dalal, A., Gopal, M., Vishvakarma, S. K., & Chouhan, S. S. (2019). Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications. AEU-International Journal of Electronics and Communications, 104, 10-22.
[12]. Reviriego, Pedro, Salvatore Pontarelli, and Anees Ullah. "Error detection and correction in SRAM emulated TCAMs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27.2 (2018): 486-490.

View PDF