Design and Implementation of Reliable VLSI-Based EDAC Schemes for Aerospace System Integrity

Paper ID: EIJTEM_2025_12_3_83-90

Author's Name: Dr. Hymavathi K, Dr. Farha Anjum, Dr. Mohammad Iliyas

Volume: 12

Issue: 3

Year: 2025

Page No: 83-90

Abstract:

Turbo codes represent an advanced class of error correction codes renowned for their capability to approach the Shannon limit, thereby ensuring exceptional data integrity in modern communication systems. Their strong error resilience makes them highly suitable for mission-critical applications, including space communications and next-generation wireless networks. This paper presents a high-performance VLSI architecture for the efficient implementation of a turbo decoder, designed to balance throughput, latency, and hardware efficiency. The proposed architecture integrates Soft-In Soft-Out (SISO) decoding units with interleaving and deinterleaving modules, all operating based on the Maximum-a-Posteriori (MAP) algorithm. The utilization of the MAP algorithm substantially enhances decoding accuracy while reducing the required number of iterations, resulting in higher throughput and lower latency. On the encoding side, the system employs a dual Recursive Systematic Convolutional (RSC) encoder in conjunction with a pseudorandom interleaver. This configuration improves the statistical uniformity of encoded sequences and mitigates the occurrence of low-weight input patterns, thereby strengthening the overall error-correction performance. The proposed design thus provides a reliable and hardware-efficient solution for high-speed communication systems requiring robust Forward Error Correction (FEC) capabilities.

Keywords: Turbo Codes, VLSI Architecture, MAP Algorithm, SISO Decoder, RSC Encoder, Interleaver.

References:

[1]. J. G. Proakis and M. Salehi, Digital Communications, 5th ed., McGraw-Hill, 2007.
[2]. S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed., Pearson, 2004.
[3]. C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo codes,” Proc. IEEE Int. Conf. Commun., 1993, pp. 1064–1070.
[4]. J. Hagenauer, “The Turbo Principle: Tutorial Introduction and State of the Art,” Int. Symp. on Turbo Codes and Related Topics, 1997.
[5]. L. R. Bahl et al., “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inf. Theory, vol. 20, no. 2, pp. 284–287, Mar. 1974.
[6]. A. J. Viterbi, “Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,” IEEE Trans. Inf. Theory, vol. 13, no. 2, pp. 260–269, Apr. 1967.
[7]. M. Valenti and J. Sun, “The UMTS turbo code and an efficient decoder implementation suitable for software-defined radios,” Int. J. Wirel. Inf. Netw., vol. 8, no. 4, pp. 203–215, Oct. 2001.
[8]. Y. Sun and J. R. Cavallaro, “Efficient hardware implementation of a highly-parallel turbo decoder,” IEEE Trans. VLSI Syst., vol. 14, no. 10, pp. 1032–1045, Oct. 2006.
[9]. G. D. Forney, “The Viterbi algorithm,” Proc. IEEE, vol. 61, no. 3, pp. 268–278, Mar. 1973.
[10]. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inf. Theory, vol. 20, no. 2, pp. 284–287, 1974.
[11]. M. Valenti and J. Sun, “The UMTS turbo code and an efficient decoder implementation suitable for software-defined radios,” Int. J. Wirel. Inf. Netw., vol. 8, no. 4, pp. 203–215, Oct. 2001.
[12]. J. G. Proakis and M. Salehi, Digital Communications, 5th ed., McGraw-Hill, 2007.
[13]. S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed., Pearson, 2004.
[14]. P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583–602, June 2003.
[15]. M. Nicolaidis, “Design for soft error mitigation,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 405–418, Sep. 2005.
[16]. R. Gallager, “Low-density parity-check codes,” IRE Trans. Inf. Theory, vol. 8, no. 1, pp. 21–28, Jan. 1962.
[17]. J. L. Massey, “Reed–Solomon codes and their applications,” IEEE Commun. Mag., vol. 25, no. 9, pp. 24–33, Sep. 1987.
[18]. P. Reviriego et al., “A new ECC scheme with reduced power consumption for embedded DRAMs,” IEEE Trans. VLSI Syst., vol. 19, no. 8, pp. 1429–1433, Aug. 2011.
[19]. S. Rezgui, R. Velazco, and B. Granado, “Radiation testing and fault injection techniques: complementary approaches to assess digital systems reliability,” Microelectronics Reliab., vol. 76–77, pp. 503–506, Dec. 2017.
[20]. R. Naseer and J. Draper, “Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs,” IEEE Int. SOC Conf., 2008, pp. 91–94.
[21]. T. Kalavrouziotis et al., “Design of fault-tolerant reconfigurable FPGA systems for aerospace applications,” Microelectronics J., vol. 39, no. 9, pp. 1095–1105, Sep. 2008.

View PDF