Low-Area and Low-Power Threshold Implementation Design Technique for AES S-Box

Paper ID: EIJTEM_2025_12_4_66-72

Author's Name: Popshetwar Santhosh Kumar, Adiboina Venugopal

Volume: 12

Issue: 4

Year: 2025

Page No: 66-72

Abstract:

The Advanced Encryption Standard (AES) algorithm is one of the most widely adopted cryptographic standards for securing digital communication. Among its submodules, the Substitution Box (S-Box) plays a vital role in providing nonlinearity and resistance against differential and linear cryptanalysis. However, conventional S-Box implementations using Look-Up Tables (LUTs) or composite field arithmetic suffer from significant area overhead, high dynamic power consumption, and increased delay—making them less suitable for resource-constrained embedded and IoT devices. This paper proposes a novel threshold logic–based design technique for AES S-Box that minimizes both area and power without compromising functional accuracy. The proposed approach replaces conventional logic structures with threshold-based gate mappings, reducing transistor count and switching activity. The design is synthesized and verified on FPGA and ASIC platforms, demonstrating substantial improvement in power, area, and propagation delay compared to existing architectures. The results confirm that threshold logic can be effectively utilized for lightweight cryptographic hardware, providing an efficient balance between security and implementation cost.

Keywords: AES S-Box, Threshold Logic, Low Power Design, Low Area VLSI, Cryptographic Hardware, FPGA Implementation, Energy-Efficient Design

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