Leveraging Artificial Intelligence and Automation for Effective Lot Disposition and Quality Control in Semiconductor Manufacturing

Paper ID: EIJTEM_2019_6_4_29-35

Author's Name: Dileep Kumar Ghattamaneni

Volume: 6

Issue: 4

Year: 2019

Page No: 29-35

Abstract:

In semiconductor production, reliable prediction of lot quality at the Final Test (FT) step is important to guarantee product reliability and reduce operation costs. Standard models tend to be challenged by the heterogeneity and high-dimensionality of manufacturing data and hence are less effective. This research presents a new deep learning architecture combining Min-Max normalization-based preprocessing with a Spatial Incidence Adaptive Graph Embedding Neural Networks Arrangement Disintegration Convolutional Self-Attention Network (SIAGEN-ADC-SAN) for high-quality prediction. The study uses pre-processed data consisting of 42,865 backend lots gathered from 2017 to 2018 over 12 mask sets for 8-bit PIC microcontroller products. The data consist of 21 features—14 categorical and 7 numerical—across test conditions, process parameters, and physical attributes. The new architecture captures spatial relationships as well as contextual dependencies in this heterogeneous data. Moreover, the model is fine-tuned with the Grey wolf optimizer for improved convergence and predictive stability. The four-step methodology comprises data preprocessing, model architecture design, hyperparameter tuning, and ultimate evaluation, giving a complete solution for intelligent FT quality prediction. Experimental evaluation on real-world semiconductor test datasets demonstrates the proposed method achieves an outstanding accuracy of 99.9%, significantly outperforming conventional approaches.

Keywords: Semiconductor manufacturing, Spatial Incidence Adaptive Graph Embedding Neural Networks, Disintegration Convolutional Self-Attention Network, Grey wolf optimizer

References:

1. Lingitz L, Gallina V, Ansari F, Gyulai D, Pfeiffer A, Sihn W, Monostori L. Lead time prediction using machine learning
algorithms: A case study by a semiconductor manufacturer. Procedia Cirp. 2018 Jan 1;72:1051-6.
2. Munirathinam S, Ramadoss B. Predictive models for equipment fault detection in the semiconductor manufacturing
process. IACSIT International Journal of Engineering and Technology. 2016 Aug;8(4):273-85.
3. Tello G, Al-Jarrah OY, Yoo PD, Al-Hammadi Y, Muhaidat S, Lee U. Deep-structured machine learning model for the
recognition of mixed-defect patterns in semiconductor fabrication processes. IEEE Transactions on Semiconductor
Manufacturing. 2018 Apr 11;31(2):315-22.
4. Kao HA, Hsieh YS, Chen CH, Lee J. Quality prediction modeling for multistage manufacturing based on classification
and association rule mining. InMATEC Web of Conferences 2017 (Vol. 123, p. 00029). EDP Sciences.
5. Bleakie A, Djurdjanovic D. Growing structure multiple model system for quality estimation in manufacturing processes.
IEEE Transactions on Semiconductor Manufacturing. 2016 Feb 29;29(2):79-97.
6. Chen H. Novel machine learning approaches for modeling variations in semiconductor manufacturing (Doctoral
dissertation, Massachusetts Institute of Technology).
7. Kang S, Kang P. An intelligent virtual metrology system with adaptive update for semiconductor manufacturing. Journal
of Process Control. 2017 Apr 1;52:66-74.
8. Moyne J, Iskandar J. Big data analytics for smart manufacturing: Case studies in semiconductor manufacturing.
Processes. 2017 Jul 12;5(3):39.
9. Su TJ, Chen YF, Cheng JC, Chiu CL. An artificial neural network approach for wafer dicing saw quality prediction.
Microelectronics Reliability. 2018 Dec 1;91:257-61.
10. Wang J, Zhang J, Wang X. A data driven cycle time prediction with feature selection in a semiconductor wafer
fabrication system. IEEE Transactions on Semiconductor Manufacturing. 2018 Jan 1;31(1):173-82.
11. Wang J, Zhang J. Big data analytics for forecasting cycle time in semiconductor wafer fabrication system. International
Journal of Production Research. 2016 Dec 1;54(23):7231-44.
12. Melhem M, Ananou B, Ouladsine M, Pinaton J. Regression methods for predicting the product’s quality in the
semiconductor manufacturing process. IFAC-PapersOnLine. 2016 Jan 1;49(12):83-8.
13. Tello G, Al-Jarrah OY, Yoo PD, Al-Hammadi Y, Muhaidat S, Lee U. Deep-structured machine learning model for the
recognition of mixed-defect patterns in semiconductor fabrication processes. IEEE Transactions on Semiconductor
Manufacturing. 2018 Apr 11;31(2):315-22.
14. Faris H, Aljarah I, Al-Betar MA, Mirjalili S. Grey wolf optimizer: a review of recent variants and applications. Neural
computing and applications. 2018 Jul;30:413-35.
15. Yi X, Yao L, Yang T, George J, Johansson KH. Distributed optimization for second-order multi-agent systems with
dynamic event-triggered communication. In2018 IEEE Conference on Decision and Control (CDC) 2018 Dec 17 (pp. 3397-
3402). IEEE.

View PDF