Excel International Journal of Technology, Engineering & Management

ISSN : (Print): 2348–0378 |
(Online): 2349–8455

2.5

CiteScore

8.8

Global Impact Factor

Design of Low Power Based Efficient Multiplier for Signal Processing Applications

Paper ID: EIJTEM_2017_4_2_5-8

Author's Name: R. Parameshwaran

Volume: 4

Issue: 2

Year: 2017

Page No: 5-8

Abstract:

In this paper, I have proposed a new lower power based multiplier which requires booth encoder,12-bit CLA,3T-NAND2,NAND3,NAND4,3T-NOT,3T-XOR gates for its operation. In the existing methodology, the ‘Add-Shift’ multipliers performs with reduced speed, increased silicon area and increased power consumption when the number of shifts between partial products increases, Whereas the ‘serialparallel’ multipliers works with better power consumption and reduction in area, but its speed is comparatively reduced. Hence, in our proposed model, the number of partial products to be added is reduced by using “Modified Booth algorithm”. To achieve speed improvements “Wallace tree algorithm” can be used. Also, the area coverage is optimized by reducing the number of transistors used.

Keywords: Booth Encoder, 12-bit CLA, Wallace Tree Multiplier.

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